Power management features are common in today's high-power computing devices to conserve power and are especially useful in devices, such as laptop computers, that run on batteries. One way to conserve power is to modulate processor activity, which is typically enabled through the use of power management actuators, such as dynamic frequency scaling (DFS) or combined frequency and voltage scaling (DVFS) actuators, that scale-down processor frequency and/or voltage at certain times or in certain modes. By temporarily reducing processor activity, heat produced by the device is also reduced, thereby further conserving power needed for cooling.
Power management actuators typically can only adjust the voltage and/or frequency in set increments (or levels). As such, with conventional power management techniques that use power management actuators, such as MaxBIPS, the voltage is adjusted to the highest level at which power consumption by the processor approximates, but does not exceed, a particular power budget. See, for example, C. Isci et al., “An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget,” Proceedings of the 39th annual International Symposium on Microarchitecture (MICRO' 06), IEEE, pp. 347-358 (Dec. 9-13, 2006) (hereinafter “Isci”), the disclosure of which is incorporated by reference herein. For example, as described in Isci, MaxBIPS predicts power and billion instructions per second (BIPS) values for different combinations of power (voltage (Vdd)/frequency (f)) modes, i.e., full-throttle execution (Vdd, f), medium power savings (95% Vdd, 95% f) and high power savings (85% Vdd, 85% f), and chooses the combination with the highest throughput that meets a power budget. This however, can leave a large margin between the power budget and actual consumed power, in particular, if the power budget is just below the power that the processor would consume at the next higher voltage level (see, for example, FIG. 1, described below). Thus, in many instances the processor is operated at a sub-optimal power level so as not to exceed the power budget. As a result, processor performance suffers.
FIG. 1 is graph 100 illustrating suboptimal power allocation for a processor chip from use of conventional power management techniques. In graph 100, relative power is plotted over time. The term “relative power” refers to a percentage of a maximum power consumption by the processor core. In the example illustrated in graph 100, voltage and frequency (both of which can contribute to power consumption) can be controlled in three voltage/frequency pairs or levels. The given power budget is 80 percent (%) of maximum available power. As can be seen from graph 100, more than 10% of the maximum available power is foregone at the voltage level closest to the power budget. This suboptimal use of available power also translates to suboptimal processor performance, since the lower voltage correlates to operation at a lower frequency.
Therefore, processor chip power management techniques that further improve processor performance under a given power budget would be desirable.